1. Field of the Invention
The present invention relates to a synchronization control circuit used for the synchronization of an external clock and an internal clock, a semiconductor device using the synchronization control circuit, and a control method of the synchronization control circuit.
Priority is claimed on Japanese Patent Application No. 2008-219744, filed Aug. 28, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
An SDRAM having a DLL (Delay Locked Loop) is controlled by using two internal clocks of an internal clock PCLK, which is delayed from an external clock CK (which lags behind the external clock CK in phase), and an internal clock LCLK, which leads the external clock CK (which leads the external clock CK in phase). Here, the internal clock PCLK is a clock obtained when the external clock CK is delayed due to a wiring line and the like in the SDRAM. On the other hand, the internal clock LCLK is an output clock of the DLL. For example, a control signal input from the outside at the time of READ or ODT (On Die Termination) operation is input to the SDRAM in synchronization with the delayed internal clock PCLK, and each operation is controlled in synchronization with the leading internal clock LCLK in the SDRAM. Thus, in the SDRAM, it is necessary to perform a change operation (synchronization) between clocks with different phases for a predetermined signal.
Such a known technique is disclosed in Japanese Unexamined Patent Application, First Publications, Nos H9-186680 and 2000-269784. A technique of performing the change between clock signals with different timings using a flip-flop is disclosed in Japanese Unexamined Patent Application, First Publication, No H9-186680 (hereinafter, Patent Document 1). In the technique disclosed in this document, however, the divide ratio of the frequency divider 22 (FIG. 1 in Patent Document 1) is fixed. For this reason, since the latency between change clocks cannot be changed, it cannot be used as the latency counter of the SDRAM. Furthermore, a signal processor which controls the latency using a frequency-divided clock is disclosed in Japanese Unexamined Patent Application, First Publication, No 2000-269784 (hereinafter, Patent Document 2). However, a method of counting the number of latency stages in a signal processing circuit 101a (FIG. 1 in Patent Document 2), and the like, is not disclosed. Moreover, the change between clock signals with different timings is not disclosed either.
On the other hand, in order to perform the above-described change operation (synchronization) in the known SDRAM, a synchronization control circuit that performs the change operation (synchronization) by delaying the internal clock LCLK stepwise and transmitting input data to a plurality of flip-flops cascade-connected to each other in a sequential manner by the delayed clock is known.